Research And Design Of Time - To - Digital Converter In All - Digital Phase - Locked Loop

In radio frequency wireless communications, traditional frequency synthesizers are mostly realized with charge pump phase-locked loops. However technology scaling continuously degrades performance parameters like voltage swing, linear dynamic range, etc., analog and RF circuit design experiences more and more challenge. To address this problem, idea of all-digital phase locked loop (ADPLL) is proposed. Time-to-digital converter, especially high resolution ones, as the fractional phase error detector in ADPLL. enables realization of the system, becomes a very important topic for researchers.In this thesis, a high resolution TDC used in3-5GHz wide band ADPLL system is proposed, and full design flow including system analysis and design, mixed signal circuit design, hardware realization, chip measurement and verification is presented.From system analysis and design scope, main innovative ideas and achievements are listed as below:1SPEC for wideband ADPLL and fundamental loop characteristic is analyzed, frequency response modeling is established, TDC quantization noise’s contribution to system output phase noise is calculated, and SPEC for TDC is given as a result.2. According to TDC SPEC, different TDC structures and respective merits/demerits are enumerated, trade-offs between performance and cost are evaluated. Finally, two-stage TDC structure to enable both high resolution and high dynamic range is chosen.3. Design of delay line based integer TDC and self calibrated time amplifier based sub-exponent TDC are proposed, respectively. The integer TDC utilizes register arrays to sample delayed versions of start signals in the delay line and decode to a coarse quantization output; while the sub-exponent TDC amplifies input time intervals in cascading digital self-calibrated time amplifiers and produces sub-exponent output with arbiter circuit.From circuit design scope, main innovative ideas and achievements are listed as below:Layout optimization of integer TDC and clock tree driving buffer chain insertion to improve integer resolution, linearity and dynamic range. Designed a differential input master-slave D Flip-Flop with very narrow metastability time zone. Designed a high resolution time interval amplifier with controllable gain. Designed digital self calibration loop and calibration timing of time amplifier. Designed inverter based differential delay line TDC (Version Ⅱ tapeout) to further improve resolution, linearity and robustness of integer TDC. This chip is realized in TSMC65nm CMOS process, and core supply voltage is1.0V, core area is105um*85μm. Measurement result shows that operating at50Hz reference frequency, proposed TDC achieves a minimum resolution of1.2ps, dynamic range of900ps, INL/DNL of0.6LSB/0.3LSB, and core power dissipation of2mW, thus all design parameters in SPEC are met.