The Core Chip Design Of Fast Locked All Digital Phase-locked Loop

With the semiconductor technology entering the nanometer stage,the traditional RF and analog circuit design are facing great challenges,analog circuit digitization has become a trend.In order to facilitate in-chip integration,Digital PLL has been called a research hotspot,which has been paid attention to and studied by the advantages of area,power consumption and reliability.This dissertation takes the digital module of All-Digital PLL as the research topic.The theory of All-Digital PLL,loop model,frequency capture circuit and calibration circuit are studied.The main work of this dissertation can be summarized as follows:1.The structure and phase calculation method of All-Digital PLL are studied,and the mathematical model of single mode and multimode is established.Through the research of mathematical model,the factors that affect the locking time are analyzed.2.Based on 40nm-CMOS technology,a frequency and phase capture circuit for All-Digital PLL is designed,which contains Variable Phase Accumulator,Reference Phase Accumulator,Time-to-Digital Converter and its interface circuit.This dissertation designs a new type of Time-to-Digital Converter and its interface circuit,which effectively quantifies the decimal error and converts it into a binary number with fixed bit width.The simulation results show that the overall circuit works normally at 0.9 V supply voltage with 100 MHz reference frequency,where the maximum operating frequency of the Variable Phase Accumulator is 3 GHz,the power consumption of the Time-to-Digital Converter after passing through the clock gating is 0.07344 m W,which is 19.97%of the original.3.Based on 40nm-CMOS technology,a phase calibration circuit for All-Digital PLL is designed.which contains the preset number module,state detection and switching module digital filter.In this dissertation,a frequency preset technique is used to calculate the oscillator control word which is close to the expected frequency,and then adjust the working state and calibration mode of the circuit by state detection and switching module.The simulation results show that the average locking time is reduced by 0.67?s after using preset technique when the reference clock is 100MHz.This dissertation adopts 40nm-CMOS technology and adopts the top-down design method to complete the RTL level design,simulation and layout realization of the whole digital module of All-Digital PLL.The simulation results show that when the reference frequency of PLL is 100 MHz,the loop locking time is within1.6?s,and the power consumption of digital module is 0.25 m W.Digital module area of loop is 0.03 mm~2.The test results show that when the reference frequency of PLL is 100 MHz,this design can effectively capture the change of frequency and phase and adjust the oscillator control word correctly.