Research And Design Ofall-digital Phase-locked Loops With Time To Digital Converters

With the rapid development of integrated circuits, a PLL (Phase-Locked Loop) has played animportant role in VLSI circuits as an important part of modern clock generation circuits, which isused to provide on-chip high-speed clocks.Based on reading a large number of domestic and foreignliterature on phase-locked loop technologies, we firstly introduce the development, concept,classification and application of PLL, and deeply analyse the structural principle of All-Digital PLL.Then theADPLL (All-Digital PLL) with TDC (Time to Digital Converter) is designed in this paper.In this paper, the ADPLL’s system structure, sub-circuit blocks, and mathematical model areproposed, and its stability and viability are analyzed. Among them, the traditional TDC is improvedby adding the circuit of rising edge detection and expanding the width of counter, which not onlyachieves the basic function, but also improves the accuracy and the measurement range of the TDC.A FRO’s (Free-running Ring Oscillator) outputs offer a multi-phase reference signal for the DCO(Digital-Controlled Oscillator) and TDC, so the product of convention resolution is fixed to1. It notonly makes the system more stable and reliable, but also be insensitive to the number of modules toprocess, voltage and temperature. Adding the programmable arbitrary integer divider, the feedbackclock’s waveform duty cycle is fifty percent. Simplifying the structure of the traditional DCO, thebasic functions remain unchanged, and the circuit area is effectively reduced. Furthermore, thispaper focuses on introducing the design method and programming skills of all of digital circuits, thedigital integrated circuit design flow and mixed analog-digital simulation process.Based on standard0.18μm CMOS technology, the proposed ADPLL’s RTL-level modeling,simulation and the key module’s layout are implemented using the top-down design method.Simulation results show that the output frequency range from64MHz to640MHz, the frequencymultiplication factor range from27to70. When the reference frequency is10MHz, the looplocking time is within12μs.