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Research And Design Of A Novel All Digital Phase-locked Loop Working In Broadband Frequency Range

Posted on:2016-01-18Degree:MasterType:Thesis
Country:ChinaCandidate:D D LiuFull Text:PDF
GTID:2308330464961161Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
Phase-locked loop circuit is a closed loop control system that can keep the output signal and the input signal on the frequency and phase synchronization. The excellent performance of phase-locked loop makes it become the indispensable basic parts in all kinds of electronic systems. Compared to analog phase lock loop, all digital phase-locked loop not only has all the obvious advantages of digital circuit: parameter stability, strong anti-interference ability, easy integration. Etc. All digital phase-locked loop but also has solved the problem just like: nonlinear of voltage-controlled oscillator, the phase detector is inaccurate,components are easily saturated and high-order phase-locked loop is unstable Etc. And with the birth of the Field Programmable Gate Array(FPGA) as well as the theory and research about Phase-locked loop is increasingly perfect, The development of all digital phase-locked loop is more and more quickly.In this paper, base on in-depth analysis of domestic and foreign scholars’ s research achievements of phase-locked loop, In view of the problems of the traditional phase-locked loops(PLL) in complex circuit, inaccurate phase detection precision, and fixed working bandwidth, a new type of all digital phase-locked loop is proposed in this paper. Compared with the conventional ones, time to digital conversion circuit in the phase detector module can transform the phase error to high precision digital signal, and the traditional digital filter with loop structure is replaced by double-edge triggered one. in addition, a variable modulus divider is adopted to take the place of the classic fixed mode frequency divider. The system is designed by using EDA technology while the simulation is implemented under the QuartusⅡ software platform. Simulation results when the system clock is 20 MHZ show that: the phase locking range is within the frequency from 100 Hz to 1 MHz, while the lock-in time is about 10 times of the input signal cycles. In addition, it is characteristics of its broad track-in range, simple structure and easy integration, etc.
Keywords/Search Tags:FPGA, all digital phase-locked loop, time to digital conversion circuit, proportion-integral(PI) control, double-edge triggered DLF
PDF Full Text Request
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