Design Of Adaptive PI Control All-digital Phase-locked Loop Based On High-resolution TDC

With integrated circuit developing rapidly,PLL is playing a more and more important role as a key circuit to provide high quality clock.Digital phase-locked loop not only has the advantages of high reliability,low cost and small area of digital circuit,but also can overcome the problems of direct-current drift,temperature drift and device saturation,and has been used more and more widely.The traditional all digital phase-locked loop has shortcomings such as a large quantization error of time-to-digital conversion circuit,high power consumption,the loop control parameters and free oscillation frequency unable to adjust online.To solve these problems,this paper firstly analyses the working principle of all-digital phase-locked loop,familiarizes with the types of each module and its role in phase-locked loop;and then,considering the above problems,an adaptive all-digital phase-locked loop based on high resolution time-to-digital converter is proposed.Finally,the functional simulation of each module and the whole system is completed.In order to improve the accuracy and reduce the quantization error,a time-to-digital converter with two-stage structure of counting and tapping delay line is proposed,to quantify the output phase difference of the phase discriminator.In order to reduce the power consumption of the circuit,the phase detection circuit is designed to determine whether the phase of the reconstructed signal is consistent with the phase of the input signal.So enabling control signal of the digital conversion circuit are given in time.The adaptive controller can identify the frequency of the input signal through the discriminator circuit when the input signal changes abruptly,thus giving the preset number of the loop filter and the high-bit control code of the numerical control oscillator,realizing the on-line adjustment of the loop parameters,and then quickly locking the phase.The design is modeled and simulated by top-down RTL based on Verilog HDL language.The results show that each module of the designed all-digital phase-locked loop meets the functional requirements,and the quantization error of the time-to-digital conversion circuit is controlled within 0.2ns.Finally,compared with the domestic and international relevant design of all digital phase-locked loop,it shows the advantages of the design in quantization accuracy and phase-locked speed.