Research And Design Of TDC And AFC In Phase-Locked Loop

With the rapid growth of wireless communication applications,the demand for fully integrated,low-cost,low-power,and high-performance transceivers is gradually expanding.Especially in some high-speed communication methods,the quality of local oscillator signal has a pivotal impact on the communication performance.The phase-locked loop frequency synthesizer is an important module of the wireless radio frequency front-end,and its performance directly affects the overall performance of the entire wireless communication system.Time to Digital Convert(TDC)and Automatic Frequency Calibration(AFC)are important module units in the phase-locked loop,and their structure and characteristics affect the performance of the phaselocked loop.Based on this idea,a two-step time-to-digital converter with a resolution of 9.8 ps and a measurable dynamic range of 4.28 ns and a two-stage automatic frequency calibration module with a control word size of 9 bits are designed in the 40 nm CMOS process.In this thesis,the phase noise model of the all-digital phase-locked loop is analyzed,and the effect of time-to-digital converter performance on the phase noise of the all-digital phase-locked loop is discussed.Several high-performance time-to-digital converter structures are introduced,and the advantages and disadvantages of these structures are analyzed separately.Based on the above analysis,this thesis presents a two-step TDC structure.The time-to-digital converter designed in this thesis is characterized by high resolution and a wide measurement range.The two-step TDC coarse quantization stage uses a delay chain TDC structure to achieve a wide dynamic range,and the precision quantization stage uses a Vernier TDC to ensure higher resolution.During the transfer margin from the first stage TDC to the second stage TDC,a matching interface circuit structure is designed to reduce the transmission error.The two-step time-to-digital converter designed in this thesis includes a delay chain time-to-digital converter,a Vernier time-to-digital converter,and an interface circuit.The simulation results show that the resolution of the first stage TDC is 133.2 ps,the measurable dynamic range is 4.13 ns,and the resolution of the second stage TDC is 9.8 ps,and the measurable dynamic range is 147 ps.At a supply voltage of 0.9 V,it consumes 0.47 m W.This thesis also introduces several automatic frequency calibration structures used in wideband phase-locked loops.By analyzing their structural characteristics,a two-stage automatic frequency calibration unit is designed.The overall structure of the two-stage automatic frequency calibration unit and the work flow is analyzed,and the search algorithms of two different switched capacitor control words are analyzed in detail,and the binary search algorithm is used to improve the search efficiency.The two-stage automatic frequency calibration unit designed in this thesis has a coarse-tuning control word of 4 bits and a mid-tuning control word of 5 bits.Under the 40 nm CMOS process,the power consumption is 0.07 m W and the area is 73 μm×72.35 μm.