Design Of Multi-modulus Divider For Pll Frequency Synthesizer

A multi-modulus divider for PLL frequency synthesizer based on Chartered Semiconductor 0.35μm RF CMOS process is presented.First of all, the principle of divider in PLL frequency synthesizer is analyzed. Then current mode logic (CML) trigger and true single phase clock (TSPC) trigger are discussed. Considering the tradeoff among working speed, output swing and power dissipation, an improved divider based on CML trigger is designed. Divider based on TSPC trigger is optimized for high speed and low power dissipation. According to requirment of project target, a multi-modulus divider constituted with a 7/8 prescaler and P, S counters, is designed with the two proposed divider. The 7/8 prescaler is composed of CML divider, phase-switching circuit, phase-switching-control circuit and TSPC divider. In this prescaler, no glitch generate at switching, due to the change of switching order. And nor gate is introduced in phase-switching-control circuit to avoid the generation of extra pulse completely. PS asynchronous counters, which can work at 250MHz properly, are designed with TSPC divider. Finally, the layout is completed. The simulation results demonstrate that, the frequency ranges from 1.7GHz to 2GHz, and current consumption of the divider is 2.5mA. The circuits and layouts designed can work well.