Key Technique Research For RF And Millimeter-wave PLL Integrated Circuits Based On CMOS Technology

Along with the fast development of the wireless communication systems and the increased requirement for the high-speed data transmission, millimeter-wave (mm-wave) communication techniques, which have the noteworthy features of ultra-bandwidth and high-speed, have been the research hotspot in recent years and the mm-wave integrated circuits (ICs) have gained more attention among the IC designers. Previously, the millimeter-wave ICs are realized by the GaAs and InP devices, however, they are not suitable for the design of large scale integrated circuits, and the cost for the process is very high. The advantages of high integration, low cost and gradually improved characteristic frequency make CMOS process possible to implement mm-wave ICs. The design of mm-wave communication circuits based on CMOS technology will be essential to the development of wireless communication system. As a key building block of the transceiver, the frequency synthesizer determines its performances. In addition, the design of the frequency synthesizer is also the main challenge of fully integrated wireless transceiver.This work is supported by the 973-program to investigate and design the mm-wave phase locked loop (PLL) based frequency synthesizer including its key building blocks such as voltage controlled oscillator (VCO), multi-modulus divider (MMD), phase frequency detector (PFD), and charge pump (CP). Aim at synthesizer architecture and key circuit modules suitable for mm-wave application, this dissertation obtains the following results.With the increase of the operating frequency, the Q-factor of the varactor decreases rapidly and becomes lower than that of the inductor at mm-wave frequencies. The lower Q-factor of the varactor becomes the dominant factor which affects the phase noise. To obtain a low phase noise, the mechanisms for enhancing the Q-factor of the LC tank at mm-wave frequencies are analyzed and applied to optimize the proposed VCO design. Moreover, a PMOS-only cross-coupled transistor pair is adopted to provide the negative resistance, meanwhile minimizing the flicker noise and its impact on the phase noise. Fabricated in a standard 90-nm CMOS process, the proposed VCO achieves a wide tuning range of 20.1%, from 25 to 30.66 GHz and a low phase noise of-105.47 dBc/Hz at 1-MHz offset. The current of the core circuit is 10.5 mA under a single 1.2-V supply.The classification of the high-speed divided-by-2 divider is categorized in this paper. Injection locked frequency dividers (ILFDs) are chosen to realize the design of high-speed divider. To extend the locking range, a detailed theoretical analysis is described and modified structure is proposed. Fabricated in a standard 90-nm CMOS process, two high-speed wideband ILFDs are present. Measurements show that they all have good performance and the locking range is larger than 40%. Comping with other reported high-speed frequency dividers, good FOMs are attained.A high-speed programmable MMD with low power consumption is proposed in this paper. To obtain high operation frequency, the time propagation delay of the critical signals is analyzed in detail and an improved structure is proposed. For low operation current, a dynamic circuit is utilized, meanwhile, the driving buffer between the high-speed ILFD and dual-modulus divider is omitted. The ILFD can be used as divided-by-2 divider and driving buffer at the same time. Implemented in a standard 90-nm CMOS process, two high-speed programmable MMDs are present. Their operating frequency are 10.2～18.3 GHz and 25.4～ 33.5 GHz and the power consumption is 12.1 mW and 15.8 mW. Comparing with other reported high-speed frequency dividers, they have the lowest power consumption.Two essential blocks for the PLLs based on CP, a PFD and an improved current steering CP, are developed. The mechanisms for widening phase error detection range and eliminating dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from-354° to 354° and the improved CP demonstrates current mismatch of less than 1.1% and pump-current variation of 4% across the output voltage swinging from 0.2 to 1.1V.A Ka-band PLL based frequency synthesizer is proposed in a standard 90-nm CMOS process. To obtain the good performance, a modified structure is proposed to overcome the designed difficulties such as the large parasitic, serious crosstalk and driving problem which is present due to the high operation frequency at mm-wave band. Moreover, the parameters and the layout are also be optimized. To obtain accurate output frequency, EM simulators are used in the design. Under one 1.2-V supply, the proposed PLL achieves a low power consumption of 38.4 mW. The output frequencies from 28 to 32.7 GHz in step of 100 MHz are obtained. The overall phase noise performance is lower than-91.6 dBc/Hz at 1-MHz offset, and the reference spur is less than-50 dBc.