The Research And Design Of Divider Based On MCML And TSPC

Divider often work in high frequency as basic module in electronic systems,In the frequency synthesizer, the quadrature signal generation, clock generation, data recovery, and high-frequency optical fiber communication system has been widely used, Divider worked speed often become one of the bottlenecks of high-speed electronic systems, and its often has a decisive impact on system performance.Designed multimode divider mainly constituted by the nine cascade in addition to 2/3 unit in this thesis. the main in addition to 2/3 unit is high-speed trigger, In considering the design speed, area and power requirements, selected using MOS current mode logic(Mos Current Mode Logic, MCML) structure at high frequencies,using true single phase clock(True Single Phase Clock, TSPC) structure at low frequencies. In addition to 2/3 unit has a modular, easy to optimize power consumption, but the division ratio range is limited, adding the appropriate logic gate circuit and the output stage circuit, expanding the divide ratio range, the circuit not only to achieve high-speed, low-power performance, but also to realize the wide frequency division ratio.Thesis uses CSMC 0.5 ? m CMOS technology, the supply voltage is 2.5V,Loading input signal frequency is clock signal from 0.5GHz to 3GHz, Using Cadence Spectre simulator, simulation results show that the multi-modulus divider can be continuously varied within 128 to 1023, meetting the design requirements.