Design Of 0.1?3GHz Low Power 4/5 Dual-modulus Frequency Divider For CW Radar Frequency Source

Phase-locked loop(PLL)is an important part of continuous wave automotive radar,especially in recent years,the application of automotive radar sensor is more and more extensive,and its importance is increasing.As an essential module in PLL,dual-mode frequency divider not only receives high frequency signals from the superior circuit,but also provides stable and reliable AC signals for the follow-up circuit,which plays an important role in connecting the preceding and the following.Therefore,the research,analysis and design of dual-mode frequency divider has great academic value and engineering application value.The purpose of this thesis is to study and design a 0.1?3GHz 4/5 dual-mode frequency divider based on0.13mm SiGeBi CMOS technology.The dual-mode frequency divider is composed of three basic D flip-flops.And the output signals of each flip-flop are Boolean operated by combinational logic gates,then the results of the operation become the input signals of the next circuit.The D flip-flop adopts the structure of True Single-Phase Clock(TSPC).Compared with Current Mode Logic(CML)or other types of flip-flop structures,TSPC flip-flop has a wide working bandwidth and very low static power consumption,which is more suitable for the design of dual-mode frequency divider in this scenario.In order to improve the input sensitivity,an inverter chain is cascaded at the input end;in order to enhance the output driving ability,a large-scale transistor is used in the buffer stage of the output end;in order to further reduce the delay,the transistor of the combinational logic gate is embedded in the TSPC trigger.This paper introduces the topology,pre simulation results,layout design,post simulation results and chip test results of the circuit.The test results show that under the working voltage of 1.2V,the frequency division range of this 4/5 dual-mode frequency divider is 0.1?3.1GHz,the sensitivity is-3.8d Bm,and the working current is less than 1.5m A.The chip size is 685?m*575?m and the area is about 0.4mm~2.This 4/5 dual-mode frequency divider has a high operating frequency and a wide operating bandwidth.The static power consumption of its core circuit is close to 0.At present,it has been successfully applied in the phase-locked loop of CW radar,and it can also be applied in other phase-locked loop systems.It has a broad application prospect.