Research And Design Of The UHF RFID Frequency Synthesizer

With the rapid development of RFID technology, the requirement for RFIDreader’s performance is greatly improved for the market demand. The single-chipCMOS UHF RFID reader draws more and more attention since it has advantages oflow cost, low power, fast read-write speed and long recognition distance. The UHFRFID frequency synthesizer is the most important component of the reader. It hasvital significance to research on the UHF RFID frequency synthesizer. In this paper,the system of the frequency synthesizer and the key module circuits of the frequencysynthesizer including the Voltage Controlled Oscillator (VCO) and the Multi-ModulusDivider (MMD) are studied and improved after reading literatures about the frequencysynthesizer. It is mainly to deal with the problems about design complex, locking time,and power dissipation. The main contents of this article are as follow:(1) A new P&N-MOS coupling QVCO with the current reused structure isproposed for low-power applications. In this proposed circuit, the current-reusedVCO is adopted, which greatly reduces the power. For the current-reused VCO, asimple P&N-MOS coupling way is proposed, and the quadrature signals are achievedby this coupling way. The proposed QVCO is simulated by Cadence and thesimulation results show that this QVCO dissipates1.92mW and it has good outputquadrature waveforms.(2) A low-power and large output load driving capability MMD is proposed. Inthis proposed circuit, The True Single Phase Clock (TSPC) technology is used and theTSPC D flip-flop with an AND gate embedded is designed, which significantly lowersthe power dissipation of the MMD. A duty cycle optimization circuit is added at theoutput stage of the MMD, which improves the output load driving capacity. Theproposed MMD is simulated by Cadence and the simulation results show that thisMMD disspates3.72mW and the output duty-cycle is50%.(3) A simple-structure and fast-locking frequency synthesizer is designed for thesingle-chip UHF RFID reader. In this designed frequency synthesizer, the MMD withthe output duty cycle optimized is adopted in this frequency synthesizer, whichgreatly reduces the design complexity and improves the operating speed of thefrequency synthesizer. The designed UHF RFID frequency synthesizer is simulated in chartered0.18μmCMOS process by Cadence. The simulation results show the locking time of thisfrequency synthesizer is less than10μs. It has the advantage of fast-locking speed.