Research And Design Of Sigma-Delta Fractional-N Frequency Synthesizer

The frequency synthesizer is a key building block of radio frequency front-end for wireless communications and its performance determines the frequency selectivity of radio frequency receivers. The fractional frequency synthesizer, which is based on Sigma-Delta modulation and targeted for 3G communications, is researched in this thesis.The thesis first illustrates the significance of the application of Sigma-Delta modulation in the implementation of the fractional frequency synthesizer. Then the general specification parameters are introduced and the difference and conversion methods among different definition forms for the same parameter are clarified.The intrinsic non-linearity of the Sigma-Delta modulator makes its theory research very hard. Based on the research on the limit cycle and stability of general Sigma-Delta modulator, more research is focused on the limit cycle and stability of the third order Sigma-Delta modulator which is eligible for the application of the fractional frequency synthesizer. The non-linearity resulting from the frequency synthesizer loop folds the high frequency noise of the Sigma-Delta modulator into low frequency and degrades the output in-band phase noise of the frequency synthesizer. A simple weighted entropy method is proposed to figure the sensitivity of the Sigma-Delta modulator to non-linearity.The loop filter is an area bottleneck of the monolithic integrating frequency synthesizer. Based on the research on the dual-path filter and the capacitance multiplication technique, an implicit dual-path filter is proposed in the thesis. The implicit dual-path filter combines the advantage of both dual-path filter and capacitance multiplication technique and improves its performance without sacrificing the area. Furthermore, the performance of low frequency output noise and the applicable frequency range of the filter are improved by employing trans-conductor enhanceing technique.Based on the research on the phase switching dual-modulus prescaler, a direct multi-modulus frequency divider is brought out by modifying the phase switching dual-modulus prescaler. The output spike of the frequency divider is eliminated by adopting the inverse switching strategy, which makes the multi-modulus frequency divider simpler and more robust.The voltage controlled oscillator is one of the key building blocks in the frequency synthesizer and its phase noise directly affects the output phase noise of the whole frequency synthesizer. The non-ideality of the phase/frequency detector and the charge pump, such as dead zone and current mismatch, affects the output in-band phase noise of the frequency synthesizer. The most eligible one is selected for the target application by comparing several methods of rejecting non-ideality. In order to analyze and validate the performance of the frequency synthesizer, it is necessary to make models for the whole frequency synthesizer. An independent frequency domain model and an independent time domain model are made for the Sigma-Delta fractional frequency synthesizer. The frequency domain model, based on the model proposed by M. H. Perrott turns to be more open through extension and is able to analyze phase noise as well as the influence of other non-ideality. Moreover, the frequency domain model can receive parts of results from other simulator to verify the performance of the whole frequency synthesizer. The time domain model is driven by events, which eliminates the conflict between simulation accuracy and simulation timeA Sigma-Delta fractional frequency synthesizer is designed with TSMC 0.18μm MM/RF 1P6M Salicide 1.8V/3.3V process to validate the research conclusion of the thesis. The achievable phase noise is–86dBc@10KHz, -102.5dBc@100KHz and–125.2dBc@1MHz which meets the specification except for a little violation at 100KHz. The frequency switching time is rough 100μS. The chip occupies an area of 2.0×2.4 mm2 with power consumption 20mW from 1.8V power supply.