Design Of High Speed Low Power Divider And Triple-modulus Prescaler

Since the United States began to use the GPS in 1964,it has begun to provide real-time,allweather and global navigation services for the three major areas of land,sea and air.Since then,global positioning standards have been adopted for positioning and timing.China began to build the Beidou satellite navigation system in 2000.After more than ten years of construction,it has developed from the active positioning of the BD-1 with short-message to cover Asia Pacific region of the BD-2 with passive positioning,and is in the process of building a global network for the BD-3.The biggest difference between the RF transceiver chip and other RF communication chips in the global satellite navigation system is that it takes a long time to work without interruption.The power consumption of the navigation RF transceiver chip directly determines the life time of the mobile navigation device,so the low power consumption becomes the important indicator of current design.This theis first introduces the basic principle of the frequency synthesizer in the image rejection receiver,and gives the specific structure design.Secondly,it analyzes and compares the main structure and working principle of the frequency divider.Based on this,the I/Q divider based on the current mode master-slave latch structure is designed.It outputs four quadrature differential signals with a phase difference of 90°.the I/Q phase error is less than 1.98°,and operating current < 1.98 mA.Finally,the working principle of the dual-modulus prescaler and the three-modulus prescaler is mainly analyzed,and the key technologies based on the phase-switch prescaler are analyzed in detail,and completed the 16/16.5/17 tri-modulus prescaler.The design has a minimum continuous frequency division ratio of 256,operating current <1.41 mA,and a delta-sigma modulator with a halved quantization level reduces the contribution to the output phase noise by 6dB.The I/Q divider and 16/16.5/17 triple-modulus prescaler in this theis use TSMC 0.13?m RF CMOS 1p6 m process with layout area of 60?m×53?m and 77?m×54?m,respectively.The results of both pre or post simulations show that the I/Q divider and the 16/16.5/17 triple-modulus prescaler work well under various process angles,temperatures,and supply voltage conditions,and all the indicators meet the design specifications.