Design Of Delay Locked Loop For Clock Generator

Delay Locked Loop is an important part of the clock generator. Compared with phase locked loop, delay locked loop apply a voltage controlled delay line instead of voltage controlled oscillator.Its clock jitter is lower and the system is more stable. Thus, delay locked loop has a more extensive application prospect. In this paper, I conduct an investigation about current research of delay phase locked loop and have a depth analysis about the working principle of the system and major modules. On this basis, I design a high-frequency and low jitter performance delay locked loop which can be applied in clock generator.In this paper, delay locked loop consists of five parts: phase detector, charge pump, loop fliter,voltage controlled delay line and bias. The dynamic logic style PD is adopted to avoid the dead-zone problem. It not only improve the operating speed, but also has a lower power. And for the burrs appeared in output clock wave of the system, when the loop is locked, we apply four inverters to separate the output clock from the phase detector to suppress that. Charge pump with a folding amplifier achieve a high match of charging and discharging current, which effectively reduces the jitter. Voltage control delay line is composed of differential delay units, and this type of circuit,suppressing common mode noise and output clock jitter, is no need to implement a replica bias circuit for it. Voltage controlled delay line is powered by low-dropout linear regulator, which reduces the change of the delay time caused by supply voltage fluctuations. Filter has an initial voltage generated by divider circuit to avoid locking system errors. The voltage divider circuit can be controlled by starting control circuit or an external switch chip.Delay locked loop is designed on SMIC 0.18μm CMOS process, using Spectre circuit simulator to simulate the system and modules. Simulation result shows when the power supply voltage is 1.8V,the circuit operating frequency is from 500 MHz to 750 MHz.When the output clock is 500 MHz, rms jitter is 0.576 ps, peak to peak jitter is 7.331 ps, power consumption is about 1.72mw; when the output clock is 750 MHz, rms jitter 0.332 ps, peak jitter of 4.225 ps, power consumption is about3.36 mw.