High Speed And Low Power A/D Converter Design And Research For Ir-uwb System Based On0.13μm CMOS Technology

With the rapid development of information technology, the demand for mobile communications is gradually increasing. At the same time people are more eager to be able to access to information resource efficiently. In this context the short-range wireless network technology gradually become a hot research topic. As the means of short-range wireless transmission, Ultra-wideband communication technology has low spectral density, low power, low cost and high-rate and so on. It has broad application prospects in the field of communication, consumer electronics, computer and so on. Based on IR-UWB, this paper presents a high-speed analog to digital converter (ADC) which is applied between the RF receiver and digital baseband.IR-UWB system use narrow pulse signal (usually up to the nanosecond) to transmit data. As the signal itself has high instantaneous SNR and is highly compressed in the time domain, we propose a low bit sampling method for ultra-wideband receiver. It means that we sample the received pulse signal only for1to2bits and then demodulates the received signal in the digital domain.The previous theoretical research show that in Additive White Gaussian Noise channel the single-bit sampling receiver only has2dB SNR loss compared to the best SNR of full precision matched filter receiver. The whole system can accept such design specifications. So this ADC design is a single-bit resolution. Also UWB system require ADC sampling rate of not less than2Gsps, so our work is a single bit, sampling rate2Gsps speed low-power ADC.According to the circuit indicators that UWB system requires and several typical ADC structure, we conclude that flash ADC is the ideal choice for IR-UWB system.The proposed ADC uses the non-time-interleaved architecture without channel mismatch calibration circuit. And in order to meet the UWB system for high-speed low-power ADC requirements, the circuit structure of our analog portion use a logic low swing differential current mode. In order to solve the mismatch problem between the high-speed ADC and low speed digital baseband, we design a parallel data deceleration circuit which can convert the high-speed serial data into parallel data output of500Mbps.This chip is completed by adopting TSMC0.13μm CMOS process.The chip test results show that the reachable sampling rate is2.5Gsps and the LSB of the single bit AD converter is10mV. The core circuit area of the chip is0.72mm2.The power consumption is42mW with1.2V power supply.