Design On Static/Dynamic Calibration And Nano-CMOS Robust Implementation For High-Speed High-Accuracy Digital-to-Analog Converter

High speed and high accuracy digital-to-analog converter (DAC) as the core device in the field of wireless communication and digital TV, directly affects the performance of the whole system. But with the application of DAC requirements gradually to the high sampling rate, high precision and high signal bandwidth mismatch error, static and dynamic mismatch error becomes the bottleneck restricting the performance of dac. And in the nanometer CMOS process, design of DAC is faced with many new problems.Under this background, this paper mainly studies the high speed and high accuracy digital-to-analog converter static and dynamic mismatch calibration method, and a digital-to-analog converter in nanometer CMOS process robust design method.In the aspect of static mismatch error calibration, this paper proposes a random clock full calibration method, which can eliminate the current source static mismatch error. The method is based on the background self-calibration method, using the op amp feedback loop as a calibration circuit. The mismatch current sources are calibreated one by one in the control of a random clock. The LSB current source array are used in current splitting structure, which can avoid the redundancy current source array introduced and achieve the calibration of MSB and LSB current source. In0.18μm CMOS process,14-bit200MS/s current steering DAC is implemented. At2MHz output signal, the SFDR has24dB improvement in the before and after calibration, reaching above80dB, and then the proposed calibration method is fully validatedIn the aspect of dynamic mismatch error calibration, cell-dependent delay differences and output-dependent delay differences of the DAC are modeled and deep theoretical derivation. For the output-dependent delay differences, the output-aware adjustment calibration is proposed. And proposed method is applied to a14bits current steering DAC. The simulation results show that, the whole Nyquist frequency bandwidth, SFDR is increased at least10dB. This paper also presents a method called as matching channel dynamic, aimed at eliminating dynamic mismatch between channels in the time-interleaved DAC. To simulate and verificate the proposed dynamic channel matching method, a Hbits time-interleaved digital-to-analog converter is designed, when the output signal close to the Nyquist frequency, SFDR can improve15dB before and after calibration.In the aspect of nano-CMOS process design, this paper proposes a robust design method of multi-channel DAC overall structure, including design methods of the current sources, latches and switches, and bias circuits in the channel and inter-channel. The robust design method can effectively avoid the effect of STI and WPE, and overcome the process fluctuation in the channel and inter-channel mismatch errors. A40nm CMOS500MS/s10-bit triple-channel DAC is implemented. The experiment test results show that for three channels, the maximum INL is0.58LSB, the maximum DNL of0.42LSB, and the minimum value of SFDR is56.98dB. The single channel and the channels between each other have achieved good matching.