Research And Implementation Of Turbo Codec

Turbo-code was borned in 1993, which has found its way in wireless communication for its outstanding performance. Many Wireless Communication Standards Organization select Turbo-code as their channel codes, like 3GPP LTE, WiMAX, etc. As the developing of VLSI technology, the Turbo-codec meet different system requirements has been implemented in hard-ware.The generally used decoding algorithm for Turbo-code include siso-Viterbi, LogMap, Max_Log_Map and so on. This thesis select QPP as the interleaver and use Max_Log_Map as the decoding algorithm for which has a more acceptable complexity and performance.Also, some important parameters of Turbo-code like the length of interleaver, iteration times, quantitative of datas and normalized have been anylysised in Matlab. Then, a RTL design of Turbo-code has been done by Verilog-HDL with those special parameters above. Under the platform of FPGA,this thesis get a Turbo encoder with the maximum clock rate at 200MHz, by the optimization for QPP's critical path. As for Turbo-decoder, some ctitical path in SISO'S ACSO cicurit were been parallelzied, and the sliding-window method was employed to reduce the area of RAM and the dual-buffer mechanism was applyed in the Turbo-codec. Finally,this thesis get a Turbo-decoder with the throughput at 9Mbps.