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High Throughput Encoding And Decoding Algorithm On Turbo Product Codes And FPGA-Based Implementation

Posted on:2015-03-29Degree:MasterType:Thesis
Country:ChinaCandidate:J F LiangFull Text:PDF
GTID:2308330464468651Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Turbo Product Code(TPC), proposed in 1994, has aroused wide concern among researchers for its excellent performances. As an efficient forward error control(FEC) channel coding technology which has a great deal of flexibility in the rate, decoding performance and hardware complexity aspects, TPC has a bright prospect.With the rapid development of communication technology, there is an increasing demand for high-speed data rates. Traditional serial TPC decoder requires fewer resources, but it has long latency, which is difficult to meet the requirements of high speed. As a consequence, people have turned to parallel decoders. The features of TPC make it easy to increase the degree of parallelism, but multi-row(multi-column) parallel decoding requires large amounts of storage resources and it is difficult to control. In this paper, we propose a new parallel decoder, which greatly improves the throughput of TPC decoder. To realize high speed, a variety of design methods are proposed in this paper such as comprising a new decoding structure to reduce the latency between row and column decoding; designing a component code decoder which can process a row of code each clock; using quicksort method to realized latency reduction when searching for the most unreliable bit; using quicksort method which can reduce the latency when comparing the relevant metrics of the candidate codewords for the decision codeword and competition codeword. These techniques can significantly improve the throughput of the decoder.On the basis of the cooperative research project with CETC-10,three TPC encoders and decoders of different rates have developed on Xilinx Virtex-5 xc5vlx330 using VHDL as the development language:(32, 26, 4)?(32, 26, 4) TPC,(64, 57, 4) ?(32, 26, 4) TPC and(64, 57, 4) ?(64, 57, 4) TPC, which are made into a rate-compatible decoder distinguished by an input signal ‘mode’. The total resource is just slightly higher than the single codec which has the highest resource utilization. We had it tested and the throughput of the three TPC decoders are respectively 315 Mbps, 502 Mbps and 1083 Mbps, which realized the Gbps throughput decoder.
Keywords/Search Tags:Turbo Product Codes, Parallel Decoder, Chase Algorithm, FPGA, Rate-compatible Encoder and Decoder
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