Turbo Coding, Fpga-based Realization

The aim of this paper is to implement the encoder and decoder of turbo codes with FPGA. The encoding and decoding algorithms and how to implement them with hardware language have been discussed in the paper.Firstly, the paper introduces the theory of encoding and decoding of turbo codes. Referring to Telemetry Channel Coding Recommendation for Space System of CCSDS, A series of resolutions for the encoder and decoder are developed for adapting to frame size, code rate, interleaving algorithm, frame synchronization and pseudo-randomizer. Comparisons of their performances and implementation complexities are performed. A Max-log-MAP turbo decoder is designed to offer performance-complexity compromise. The whole system of encoding and decoding is partitioned into several functional modules with top-down technology of FPGA design.A 12-bit fix-point turbo decoder based on Max-log-MAP algorithm is then designed and simulated using Verilog HDL. The model is verified by comparing its performance with those obtained from a Matlab implementation of the same turbo model.Afterwards some kind of technology, such as sliding-windowing, normalization, stopping criterions and pipelining, are applied to improve the performance of the turbo decoder. Simulations and synthesis with the target device of Xilinx Virtex-Ⅱ 500 have been illustrated that the performance of the decoder has not been degraded greatly and that the higher throughout of the decoder is achieved with smaller storage area.