FPGA Implementation Of Pure Interger LOG-MAP Turbo Encoder/Decoder

Errors often occur in sink due to the inevitable channel noise during the signal transmission. Therefore, as the pivotal technology, error-control has become a hotspot for many years. In 1993, a group of people led by C.Berrou brought forward the well-known Turbo code that has the error performance approaching Shannon-limit. The Turbo code is generally regarded as a landmark in the history of channel coding. Nowadays, Turbo code has been adopted as one of the standards in 3G due to its excellent performance.Owing to the interleaving and de-interleaving of information sequences during the iterative decoding of Turbo code, the considerable decoding delay is inevitable and the construction of Turbo decoder also gives large operations in its decoding arithmetic. So, how to reduce the decoding delay in the implementation of Turbo encoder/decoder is very important and has great value. The methods to resolve the long delay problem nowadays are mainly to design more efficient decoding algorithms, as well as to employ parallel decoding strategy at the expenses of hardware overheads.This thesis presents a turbo decoding implementation using only pure integer operations based on FPGA technology. By adopting pipeline techniques, module reuse and other optimization techniques, decoding speed can be increased and the resource consumption can be reduced significantly. The whole design is based on Verlog HDL language with Stratix II series chipsets of Altera.This thesis is divided into six chapters. The first chapter introduces Turbo code, FPGA hardware and related implemental background. The second chapter presents the fundamentals of Turbo code, structure of encoders and interlevers. The third chapter discusses the structures of decoders and compares by simulation the traditional MAP algorithm, LOG-MAP algorithm, and the new LOG-MAP algorithm based on pure integers. The fourth chapter describes the FPGA implementation of the new pure integral LOG-MAP decoding algorithm, and the fifth chapter presents the performance test of the FPGA implementation of Turbo decoder. Finally, the last chapter concludes the thesis and presents the future work to further improve the design.