Implement Of Turbo Codes Encoder And Decoder Based On FPGA

Turbo codes are a kind of coding schemes which could approach the Shannon’scapacity bound, Because of its excellent performance, Turbo codes have been widely usedin the communications. and has become a hot research subject of error-correcting codes.With development in nearly twenty years, it become one focus studies that how to use thehardware to achieve effective Turbo codes．In order to implement the encoder and decoderof Turbo Codes with FPGA, this paper discuses the encoding and decoding algorithms andhow to implement them with hardware.Firstly, the paper based on the theory of introduces the Turbo coding and decoding,focusing on the decoder, detailed analysis three commonly used decoding algorithm ofMAP, Log-MAP and Max-Log-MAP, and has also analyzed the major factors affectperformance of Turbo Decoding and simulated by MATLAB. This laid a theoreticalfoundation for which algorithm and parameters should be used in the hardwareimplementation.Secondly, we select the Max-Log-MAP decoding algorithm to carry out Turbo codesdecoder in this paper, For the realization of interleaver and deinterleaver, representation offixed-point data and the main computing unit of sub-decoder’s Max-Log-MAP algorithmon FPGA design. The key is our paper use two sets of memory so that the twosub-decoders alternately work that can reduce the delay effectively and improve thedecoding speed．Finally, during the FPGA implementation, we choose the Cyclone II of Altera’s deviceto complete the Turbo codes simulation The entire system is divided into differentfunctional modules by analyzing the Turbo codes functions，and then to realize each of thedifferent modules with the Verilog language and schematic diagrams. the paper describesthe design idea of the various modules in detail，after each module design is completedand verified the correct function of them integrate this module, simulate and test theperformance of the entire system．...