The Design And Implementation Of Turbo Encoder And Decoder Based On FPGA

Since Turbo code was proposed in 1993, it has received great attention and become a research hot spot due to it's near Shannon limited good coding performance. With the continuous research and the development of technique, Turbo code has begun to apply in the real communication systems. Now, how to implement the Turbo encoder and decoder with hardware effectively has become a research hot spot.In order to implement the Turbo encoder and decoder based on FPGA, firstly, this thesis has analyzed the principles of Turbo code and the 3GPP Turbo encoder. Secondly, this thesis has carried on detailed theory analysis MAP algorithm, Log-MAP algorithm and Max-Log-MAP algorithm, and has also analyzed the major factors affecting the Turbo coding performance with MATLAB simulations. And thirdly it determined the factors those met performance demanded through simulation.Based on analysis and comparison the results of simulation, this thesis has designed the Turbo encoder and verified the encoder. It has adopted Max-Log-MAP decoding algorithm to carry on the design and implementation of Turbo code based on FPGA and verified it. And finally has designed the whole communication and debugged it. Data quantization, fixed-point presentation, the FPGA design of key compute modules in Max-Log-MAP sub-decoder and time sequence control in Turbo decoder of 3GPP standard have been discussed. Finally, a fixed decoding length Turbo encoder and decoder based on FPGA has been designed, and function timing verification and FPGA fixed-point simulation has been separately carried on with ModelSim and MATLAB.