Research And Development Of Turbo Codes Encoder And Decoder Based On FPGA

Turbo codes are a kind of coding schemes which can approach the Shannon's capacity bound.Because of its excellent performance,Turbo codes have been widely applied in the communications. The development of mobile communication technology proposed a very high demand to Turbo codes. Long term evolution(LTE) can reach a throughput of 100Mbps in a downlink and 50Mbps in an uplink respectively. So how to implement Turbo encoding and decoding of LTE in the high performance hardware become the focus of people's research. In order to implement the encoder and decoder of Turbo codes with FPGA.The encoding and decoding algorithms and how to implement them with hardware have been discussed in the paper.This paper firstly derived MAP decoding Algorithm,LOG-MAP algorithm and MAX-LOG-MAP algorithm for the calculation methods and formulas. Then carried on detailed theory analysis and computes complexity comparison of three decoding algorithms and has also analyzed the major factors affect performance of Turbo Decoding and simulated by MATLAB . This laid a theoretical foundation for which lgorithm and parameters should be used in the hardware implementation.According to simulation result, completed the FPGA design and implementation of Turbo decoder use MAX-LOG-MAP algorithm .And through the sliding-window and efficient normalization algorithm significantly reduces resource consumption and decoding delay without reduce performance. Improved two SISO scheme allows just use one single SISO module reuse to reduce resources consumption by nearly a half.Research on the traditional feedback iterative decoder and analyze the causes of the low throughput and design a pipelined decoder, which will increase throughput to reach the standard of LTE protocol. Finally, the decoder hardware platform has been tested and compared with the theoretical value to verify the correctness of the results.