Research Of Turbo-Code Encoder And Decoder And FPGA Implementation

Due to its performance to achieve the Shannon limits, low complexity and characteristic of high-speed encoding and decoding, Turbo code becomes to the research focus of communication fields, and is widely applied to the 3g and 4g mobile communications with its excellent channel coding speciality. FPGA(Field Programm-able Gate Array) is widely used for communication system because of its excellent agility of design, reusability and short development circle, etc.This article mainly starts from basic principle and algorithm of Turbo-code channel encode and decode system, and on this basis to provide an overall design of codec, including two parts of encoding and decoding. The encoding part includes source modules, interweave modules, and component encode modules, puncture table modules, multiple connection modules of CRSC. The decoding part includes data conversion modules, de-multiple connection modules, and component decode modules, interweave and de-interweave modules, hard decision modules of Max-Log-MAP algorithm.This system uses Synplify to synthesize each module, to accomplish the design of Turbo-code RTL(Register-Transfer Layer), and adopts Modelsim to simulate the module and system. When simulation result meets the design requirements, the designed Turbo-code encoding module is downloaded to Spartan-3E FPGA hardware platform, which belongs to Xilinx, to proceed system testing, and contrast and analysis the results of system hardware testing and the Modelsim simulating.The result of system simulation and testing shows that the designed Turbo-code codec can realize correctly the function of encoding and decoding modules, and the system comprehensive testing is successful, since the data of decoder output and encoder input is consistent. Under the condition of leaving out wireless channel simulation module, software simulation result of encoder and decoder is correct, hardware testing result of encoder is correct.