Design And FPGA Implementation Of Turbo Codes

Turbo codes are a class of coding schemes which can approach the Shannon's capacity bound. It is for their outstanding performances that Turbo codes have been widely used in telecommunications. The aim of this paper is to implement the encoder and decoder of Turbo codes with FPGA. The encoding and decoding algorithms and how to implement them with hardware have been discussed in the paper.Firstly, the theory of the encoding and decoding of Turbo codes are introduced, followed by an analysis of some factors that can affect the performance of Turbo codes and some simulations with C language. Secondly, in aspect of the FPGA implementation, a study of the algorithm is given according to the feature of the FPGA. And the sliding-window method is used to the algorithm to modify it, which can reduce the resource requirement and the processing delay. The modular design method is applied in the whole system. According to the complicated problems of the control in the decoding, the three-layer control mode is used. Therefore the joint debugging of the whole system will be much easier and the relationship among the modules can be simplified. A tradeoff is made between the hardware implementation complexity and the processing delay when designing and implementing each sub-module, with the aim of increasing the generality and reducing the computational complexity. Finally, the codec is verified on the practical hardware platform, which achieves an ideal result.