Design Of Turbo Decoder For Satellite Communication

During these years,as the progress of satellite communication technology,people are demanding more and more the quality of satellite communication,Channel coding technology is a work like a charm way to enhance communication reliability.As an ideal code type close to the Shannon limit,Turbo code can not only show outstanding performance in a low SNR ratio environment,but also has strong anti fading and anti jamming performance.Therefore,it has also been widespread made use of the field of satellite communications,and has become a hot point in channel coding research.However,there are a great quantity of exponential and logarithmic operations in the computational process of Turbo codes,which makes the complexity of decoding operations very high,and it is very difficult to implement in hardware.In addition,due to the special encoding method of the Turbo code,decoding can be performed after receiving all the data,which consumes a lot of storage space and also brings a great decoding delay.In order to solve these problems,this paper takes low delay and low resource occupation as the realization requirements,and completes the design of Turbo decoder.This article takes the Turbo code decoder in satellite communications as the research objective,and analyzes it from two levels of decoding algorithm and hardware implementation.At the algorithm level,based on the traditional Log-MAP decoding algorithm,sliding window technology is introduced to achieve the purpose of reducing the decoding transmission delay and storage resources.At the same time,so as to decrease the complexity of the decoding algorithm,the Jacobian logarithmic expression in the Log-MAP algorithm is converted to a linear expression by linear fitting.Finally,use Matlab simulation to analyze the relevant parameters that affect the decoding performance.The simulation results indicate that along with the interleaving length increases,the coding rate decreases,and the amount of iterations supplement,the decoding performance will be enhance accordingly.At the hardware level,the decoder is designed with a field programmable gate array(Filed Programmable Gate Array,FPGA).Through synthesis and realization,the use of sliding LogMAP decoding algorithm reduces the resource occupancy rate and delay of the hardware.Compared with the traditional Log-MAP algorithm,although the Registers increase by about41%,the flip-flops,look-up tables,and embedded block memory are reduced by about 35%,33%,and 76%,respectively.In general,the resource occupancy rate of the sliding window Log-MAP algorithm is still relatively small,and secondly,the decoding delay is also reduced by about 53.65 us.Finally,the FPGA implementation result is compared with the Matlab implementation result,and the decoding performance of the two is basically the same.Therefore,while the Turbo code decoder designed in this paper maintains good decoding performance,the time delay and storage resources are also effectively reduced.