Design Of Multi-frequency Low Phase Noise Clock Generator Based On Phase Locked Loop Technology

The function of the phase-locked loop is to make the output signal of the oscillator track the change of the reference signal to achieve the frequency doubling function.The clock generator based on the phase-locked loop technology has become a key circuit in high-performance processors,analog-to-digital converters,and data recovery.In recent years,with the growing development of high-tech fields and the continuous reduction of the process size of integrated circuits,there has been an increasing demand for clock accuracy,phase noise,response speed and number of output frequency.Focusing on fast locking,low phase noise,and multi-frequency output,the design of multi-frequency and low-phase noise clock generator based on phase-locked loop technology has been completed according the process from system design to behavior model verification to circuit-level design and layout design.The main work of this article is as follows:1.Establish modular and behavioral simulations.Based on the establishment of the third-order and fourth-order phase-locked loop linear models,the stability of the system is investigated,and the positions of the poles and zeros of the loop are deduced.The relationship between loop bandwidth and lock time is studied which determines to use dynamic loop bandwidth technology to accelerate locking.Analysis of phase-locked loop noise model provides theoretical basis for optimizing phase noise.2.Key module design.In the phase frequency detector and charge pump,delay controllable units,complementary switches,op amp clamps and other structures are added to optimize the circuit and reduce phase noise introduced by non-ideal factors.The lock detection circuit can accurately detect the loop state of the phase-locked loop.The output control signal increases the loop bandwidth during the capture phase and speeds up the capture speed.It reduces the loop bandwidth after locking to better filter highfrequency noise.Dynamic loop bandwidth technology reduces PLL lock time by more than 40%.The loop filter uses a third-order structure to improve high-frequency noise suppression.The VCO of LC structure with 3bit capacitor arrays can achieve a wide tuning range while reducing noise caused by external control voltage fluctuations.The self-switching bias technology is used to reduce the flicker noise of the tail current tube,and the phase noise at 1MHz can be optimized to 4dBc / Hz.The programmable dualmodulus frequency divider is based on a dual-mode prescaler and a pulse counter.The dynamic high-speed flip-flop is designed as the basic unit to ensure the working speed of the frequency divider under high-frequency conditions.The design method of synchronous sequential logic is used to ensure accurate timing.A 20-bit third-order MASH1-1-1 sigma-delta modulator and the corresponding interface circuit are designed to implement the fractional frequency division function,eliminate decimal spurs and modulate quantization noise to high frequencies.It has the advantages of high frequency resolution,stable structure,and fast working speed.3.Overall design and results.Based on a 0.18?m technology platform,this paper has completed the overall circuit design,layout design and simulation of a multifrequency low-phase noise clock generator based on phase-locked loop technology.The supply voltage is 1.8V.The lock time of PLL os less than 2.1?s.The maximum power consumption of the overall circuit is 3.5mA.The output tuning range is 0.99 GHz to 1.55 GHz.Phase noise of PLL at 1MHz is-123.1dBc / Hz.PLL realizes 20 bit Fractional division.