Research On Characterization Of SRAM

The amount of embedded Static Random Access Memory in system-on-chip designs has been increasing rapidly which demand shorter design cycle of SRAM without any significant loss of performance. Faster and more efficient SRAM characterization will become essential since the demand increasely and diversity in SRAM. In this thesis we analyzed characterization of timing constraint for implementation of SRAM design.Traditional approach affect the time to matket since the simulation consumes too much time. Some other methods lack of much accurate in characterization of SRAM. A novel methodology was proposed to characterize timing constraint for SRAM. The methodology analyzed and extracted partial circuits that have great impact on timing constraint for simulation instead of the traditional entire circuit topology simulation approach, thereby determined more precise timing window for dichotomizing characterization of timing constraint based on the path delay calculation methodology. As a result, the methodology characterized of setup time for SRAM improves run-time without any accurate comparing with traditional approach.With the SRAM capacity increasing, the circuit scale increases dramatically. The time of Characterization for SRAM will be too expensive. But the scale of circuit simulatied in the novel methodology is Independent on the SRAM capacity. And the more precise timing window can reduce the number of dichotomizing characterization. With the circuit scale increasing and portability of design, taller and narrower lines are being laid out closer to each other. Crosstalk is important in VLSI's. We analyzed the reason,effection,model and some techniques for reduce crosstalk.