Establishment And Verification Of The Timing And Power Consumption Model For The Embedded SRAM Compiler

Embedded memory as an important part in the SoC system, its importance is increasing. First, in the SoC chip, SRAM is located in the data path on the critical path of access speed directly, which restricts the core slice; Second, because the promotion of read/write speed and the increase of storage space of an SRAM, its power consumption shares the chip total power consumption higher and high; Again, the density of SRAM directly affect the area of the chip and cost, and this can use the high level of design and the advanced technology of physical implementation to reduce the influence; SRAM has become the performance bottleneck of the development of SoC Systems, such as speed (frequency), power consumption and the area. So the customization of high-speed, low-power, high-density SRAM on the critical path is very beneficial to the improvement of the whole SoC chip performance, low power consumption and cost. People usually adopt full custom designing and SRAM compiler to produce the required memory in the industry today.This paper uses SRAM compiler to generate corresponding SRAM IP core according to the different users’ needs quickly, which uses the customizing design method to guarantee the stability of an SRAM and high performance. Users can directly read SRAM performance parameters from the Datasheet file, including timing and power consumption, etc., these parameters come from the model analytical result of parameters in the Lib library, which requests us to build the performance parameters’ model of SRAM. We have two method are analytical model and statistical model method to build the model. The design of compiler has several common problems, including the long design cycle, the higher dependence of SRAM circuit structure, the high repetitive input in the development process and the low efficiency of compiler design.Based on the research and analysis of SRAM, this paper reorganizes the parameters model involved in design of compiler and puts forward the new timing model and power consumption model according to different SRAM capacities. First, this paper uses the Hierarchical-word Decoding Architecture to solve the problem of word line overload of the large-capacity SRAM, making the load of word line reduced drastically; Secondly, for those SRAM with capacity larger than32KB, sub-module decoding technology has been applied making only one module in working status each time, which improved the performance and reduced power consumption of the SRAM; Third, this paper establishes the timing and power consumption information model for different capacity of SRAM; Finally this paper makes the Lib, Datasheet and other template files of the SRAM compiler, and also validate them. Using the proposed scheme can improve the universality and flexibility of the SRAM compiler, and can show the good from the following several aspects:the first, it chooses the architecture to achieve optimal SRAM architecture selected according to the requirements of users in order to balance area, delay, power requirements; the second, SRAM compiler can generate any type of memory as long as to provide the corresponding template file and cell library of specific process; the third, better timing and power consumption calculation method can be selected based on SRAM structure reasonable choice the parameters model in the Lib library files.