Design Of Array For Wide-voltage Timing Speculative Static Random Access Memory

In order to meet the energy efficiency requirements for SoC,wide voltage SRAM design is an increasing concern in academic.As the critical part of SRAM,SRAM array have a decisive influence on the performance of SRAM.As the power supply voltage decreases,local process variation causes the increase of the design margin.In the near-threshold region,the pessimistic design margin greatly increases the read latency of SRAM array and severely degrades the performance of SRAM.The timing speculative scheme can reduce the impact of the design margin on performance,it senses the bit-line twice,the first sensing is the speculative reading,the output data is quickly sent out after first sensing,which is used to reduce the read latency of SRAM array,the second sensing is the confirm reading,which is used for error detection.The existing timing speculative schemes have too large error detection delay in the near-threshold region,which limits its application in SoC design.This paper proposed an improved timing speculative scheme,which quickly adjusts the polarity of the input voltage of the sense amplifier after speculative reading to achieve rapid error detection.This scheme can significantly reduce the read latency of SRAM array.Compared with the conventional scheme,the read latency of the SRAM array is reduced by approximately 50% and 10% respectively at 0.5V and 0.9V.Based on the TSMC 28 nm process,this thesis designs a wide-voltage SRAM with a capacity of 256×32.The layout and post-layout simulation are completed.Compared with the conventional scheme,the proposed method achieves 36% reduction of read latency at 0.5V and 2% reduction of read latency at 0.9V.Compared with the conventional scheme,the FoM of gain is 1.96 x.Compared with the other timing speculative scheme,the proposed scheme achieves 1.75 x improvement in the FoM of gain.