The Ultra-large-scale Digital Integrated Circuit Timing Analysis And Optimization

This research is mainly intended to make a study and research for static timing analysis and optimization for digital VLSI and application of these methods for a large SoC chip.STA (Static Timing Analysis) is a full-coverage verification method, used to determine timing performance of a circuit or chip. In deep-micron process, STA become more important because it's difficult to get high coverage with functional verification. This thesis introduced basic knowledge and concepts of STA, included setup/hold time, delay modeling and calculation, timing constraint and STA flow. We studied STA for DDR memory interface and DFT circuit in detail.Based on all these knowledge and methods, we formed a STA plan for a complex, multiple-clocked SoC chip, focused on clock, memory and DFT design and analysis. With careful timing analysis and logic design, this chip taped out successfully and passed all ATE and functional testing.The thesis also introduced some popular timing optimization methods in timing-closure flow. Finally, this thesis pointed out some weak points in current STA flow and prospect of STA and optimization.