Characterization And Optimization Of 28nm SRAM Compiler

With the rapid development of mobile Internet,the information processing capacity and standby time requirement of SOC as a portable intelligent terminal is also increasing.As an important part of SOC,memory accounts for more than half of the total SOC chip area.Especially in high-performance processors,SRAM accounts for over 80% of the chip area.The performance of memory has a great influence on the SOC chip.The continuous progress of process size makes the deviation of process parameters more and more serious,which makes SRAM design more challenging,mainly in the presentation of the new current source model and the requirements of the characteristic simulation.Nowadays,more and more low-power technologies and high-speed technologies have been put forward in SRAM design,such as DVFS technology,charge pump technology and so on.While many optimization technologies have brought many conveniences,the design cycle of SRAM has been extended correspondingly,especially in the simulation link.Compared to the timing consuming SRAM design simulation cycle,these optimization techniques undoubtedly increase the simulation cycle and design cycle.The main content and research object of this paper are: Firstly,this paper introduced the structure of SRAM circuit,the design process of compiler and feature.Part two introduced the method of extracting time sequence based on key circuit is put forward,and the method is used to extract the characteristic time sequence,and compare with the sdb Setup method,Then this paper introduced characteristic of SRAM.In this part,the timing series and power consumption in the characterization are analyzed.The time series prediction was realized and the power consumption was divided according to the temperature division.Finally,the improvement of the design cycle and the simulation cycle in the SRAM design cycle is also pointed out.The last part summarized the work of this paper and forecasted the future work.