Research And Design Of Pipelined SRAM Timing Control Circuit Based On 22nm Process

In recent years,the Internet of things(Io T)technology has developed vigorously.In order to meet the high energy efficiency requirements of Io T devices,System on a Chip(So C)with a voltage as low as near the threshold region is gradually becoming a research hotspot.Static random access memory(SRAM)is an important part of So C.Its memory array is usually composed of the smallest size transistors.The small size and high density cause the degradation of its performance under low voltage to be more serious than that of logic circuits.The speed of SRAM under low voltage has become the bottleneck of chip performance.In view of the serious degradation of SRAM performance under low voltage,the use of pipeline technology in SRAM can increase the speed of its read and write operations.The timing of the existing pipeline scheme is not evenly divided,so that the clock frequency is limited by the excessively long bit line discharge time,thereby limiting the application of the pipeline technology in the SRAM.An improved pipelined SRAM timing segmentation scheme is proposed in this article,which allows the bit line discharge delay to occupy more clock cycles,thereby achieving a further increase in clock frequency.In view of the word line overlap problem caused by the improved pipelined SRAM timing splitting scheme,the four situations of continuous read operation,continuous write operation,write-after-read operation and writeafter-read operation are discussed in this article,respectively.The dual word line bitcell scheme was proposed to solve the problems in continuous read operations,the write tracking scheme was proposed to solve the problems in continuous write operations and read-after-write operations,and the idle cycle scheme was proposed to solve the problems in write-after-read operations.The specific circuit implementations of the above solutions are given in the article.Based on the TSMC 22 nm process,a pipelined SRAM with a capacity of 512×32 and its layout are designed in this article.The post-simulation results show that this scheme can effectively improve the performance of the circuit.At a low voltage of 0.6V,the maximum clock frequency and power consumption delay product of this solution are improved by 1.91 times and 34.2% respectively compared with traditional SRAM;Under the normal voltage of 0.9V,the maximum clock frequency and power consumption delay product of this solution are improved by 2.4 times and 45.5% respectively compared with traditional SRAM.Compared with similar documents published in recent years,the solution in this article also has a better performance improvement.