Research And Realization Of Timing Tracking Circuit For Wide-voltage Static Random Access Memory

With the rapid development of consumer electronics,the demand for high performance and low power System on a Chip(SoC)is growing.The wide voltage circuit design can meet the two demands of low power consumption and high performance.As an important part of SoC,Static Random Access Memory(SRAM)has become a research hotspot.In the SRAM circuit,the timing tracking module determines when the sense amplifier is enabled,which has an important influence on the overall performance and stability of the SRAM.There are two major problems in wide voltage SRAM timing tracking circuit: First,with the decrease of supply voltage,the local process variation leads to a large delay variation of Sense Amplifier Enable(SAE)signal,which deteriorates the read performance of the SRAM.Second,the design margins in different voltages are not the same,and the voltage tracking ability of traditional timing circuits is quite poor.In order to solve the two problems,the existing SRAM timing tracking schemes are investigated in detail in this thesis,and their principles and disadvantages are analyzed.Subsequently,a discharge switching timing tracking technique is proposed for wide voltage SRAM.The proposed scheme is designed mainly in two aspects: one is the process-variation-tolerant design.The proposed scheme can effectively suppress the delay variation of SAE signal by increasing the number of replica discharge bitcells.The simulation results show that,the SAE delay variation is reduced by 70% compared with the traditional scheme at 0.6V,the SRAM reading performance improves 23%,the SRAM reading power reduces 25%.Compared with other process-variation-tolerant timing tracking circuits,the SAE delay variation is reduced by at least 32%.The other design aspect is the voltage traceability design.By dynamically reducing the wordline voltage of the replica bitcell and constant threshold detection technique,the proposed scheme greatly improves the voltage tracking ability.The simulation results show that,compared with other timing tracking circuits,the voltage tracking ability of the proposed scheme is at least 1.54 x,1.98 x,2.29 x better at 0.7V,0.8V and 0.9V.The proposed scheme is implemented and tested based on SMIC 28 nm CMOS process.The test data meets the simulation expectation and the error is within reasonable limits.The test results show that the SAE delay variation of the proposed scheme is reduced by 65% compared with the traditional scheme,and the SRAM reading performance is increased by 23.6%.