Design Of Delay Locked Loop Based On Active Delay Cell

As the frequency of signal continues to increase,the characteristics of signal timing have a crucial impact on the performance of circuits.The timing characteristics of the signal can be synchronized by compensating for the delay differences between the circuits,and the delay unit has the performance of compensating for the delay differences between the circuits.In addition to compensating for the delay differences between paths,delay units have been widely used in Delay Locked Loop?DLL?,equalizer,phased antenna arrays,FIR and IIR.For DLL circuits,its function is to achieve accurate delay locking under different environmental and process conditions,often used to generate a stable signal delay.Moreover,the DLL's performance is largely determined by the delay unit.Therefore,delay units with low delay and high bandwidth and DLL have played a huge role in promoting the development of high-speed mixer circuits.In this paper,TSMC 65nm CMOS LP process is used to designing the delay unit and DLL.Considering the high power consumption and the large chip area of the delay cell structure realized by the passive inductor,the delay unit used in this project uses an active inductor parallel peaking structure.DLL is made up of the voltage-controlled delay line,XOR gate phase detector and V/I converter three basic modules.The design method of voltage-controlled delay line is composed of cascaded multi-stage delay units,the XOR gate phase detector uses a fully symmetrical V-type multiplier structure and the V/I converter is designed with a low-pass filter.The whole chip is divided into two parts:ring lock and ring test,ring locked by the DLL clock signal to achieve a quarter-cycle lock function,the loop test circuit consists of a matching circuit and a delay unit,which share a control voltage(1_?87?with the inside delay unit of DLL.The total layout area with I/O pads is 340um×790um,and the power dissipation is 31mW at a supply voltage of 1.5V.The post simulation results show that the DLL's ring input signal frequency is 4.4GHz.Nine delay units cascade to form a voltage-controlled delay line,and the relative delay between the measured delay time and the theoretical value of a single delay unit is less than 3%.DLL can be locked at different process,voltage and temperature?Process Voltage Temperature,PVT?,and its delay jitter value is less than 10%.When(1_?87?changes,delay unit's delay time can be continuously adjustable in the 5.4-7.1ps range,and the range of change is greater than 20%.The input and output matching circuit can ensure that the circuit reflection coefficient in the 0.1-10GHz is less than-10dB.When the frequency of the input signal in the adjusting loop changes within 4-5GHz,the DLL adjusts the control voltage on the delay unit,so as to realize the delay time adjustment of the delay circuit,and ultimately achieve the delay locking function.The delay unit and the DLL circuit designed in this paper can achieve low-latency and wide-band delay adjustment under different environmental and process conditions while ensuring low power consumption.This has certain significance for the research and development of high-speed mixer circuits.