Research On Key Technology Of Phase Locked Loop Applied To High-speed Interface

Phase locked loop circuits are used in a wide range of applications.In the field of highspeed interfaces,phase locked loops are especially needed to provide low-jitter and low-cost clock solutions for the whole system.Research on the key technology of phase locked loops that used for high-speed interfaces has a broad market prospect and engineering application value.Reducing the power consumption of phase locked loops,increasing their speed,reducing their jitter and reducing their production cost are all the aim of phase locked loops all the time.Because of the wide capture range and fast locking time,the charge pump phase locked loop has become the mainstream of phase locked loop applications.In this thesis,the key technology of phase locked loop for the clocking requirement of Gigabit Ethernet high-speed interface is studied.The voltage controlled oscillator which is the most important part of the phase locked loop is discussed after describing the basic theory of phase locked loop.Then,the advantages and disadvantages of different structures of the voltage controlled oscillator and different structures of the differential delay cell are all analyzed and compared in detail.A symmetric load structure of the four-stage delay cell is used and designed.Based on that,a low phase noise,ring voltage controlled oscillator with process and temperature compensation and output buffer are designed.Then,the frequency and phase detector,charge pump and divider,which are also significant in the loop,are analyzed and designed.Then,the phase noise and jitter of the charge pump phase locked loop are modeled in Matlab for system evaluation.Finally,in this thesis,the core part and the overall layout of the charge pump phase locked loop are implemented in 40 nm CMOS process with a layout area of 200μm×348μm.The postsimulation results show that the phase noise of the ring voltage controlled oscillator is-85.98 d Bc/Hz at a frequency offset of 1 MHz at 2GHz;the peak-to-peak jitter of the 125 MHz clock output from the phase locked loop is 62.24 ps,which meets the design specifications.