A Study On Multi-core Processor Clock Distribution Technology

Recent years have seen an increase in the frequency of microprocessor, as the variations of clock signal keep on almost constant ratio. This paper takes a close look at how does clock distribution eliminates on skew and jitter. It demonstrates the clock distribution scheme on the X multi-core microprocessor, showing how the deskew circuit reduces the uncertainty of global clock signal.In current ASIC design flow, clock tree is synthesized by EDA tools after placement following the multi-dimension constraints, including global skew, propagating delay, transaction time, load capacitance, and some other. Inserting deskew circuits adds more slack on global skew and propagating delay, thus accelerates the iteration convergence.The next parts focus on the physical implementation and verification of deskew circuit. Previously widely-used constructions including DLL and SMD are compared. The deskew unit NSMD modified some parts of traditional circuit, aligns output clock to reference clock in 2 cycles. On 90nm process the precision is proved less than 60ps, meaning final skew could be suppressed less than 60ps after inserting deskew circuit. Verilog-AMS based simulation on NSMD scans the scope of clock buffer delay from 0.2 cycle to 2 cycles, revealing the NSMD fits a wide range of buffer delay. Some other simulations show that variations of input clock pattern on duty cycle and frequency affects little. Verification results in PR flow also validate this design methodology.