Design Of Low Skew And Low Jitter 2.5GHz Clock Distribution Circuit

With the rapid development of modern communication technology,the clock system is working faster and faster,sampling circuits and reference circuits on the input clock signal requirements are becoming more and more stringent,and the clock jitter,transmission delay,and duty cycle will have an impact on the signal quality.To address these issues,this topic for domestic and international clock distribution circuits for in-depth research,design a multi-channel low skew low jitter 2.5GHz clock distribution circuit,the circuit provides comprehensive coverage of the frequency division function,support LVPECL and LVDS level output,jitter performance to sub-picosecond level,for FPGA and other digital circuit systems to provide low skew low jitter sampling clock and system reference clock for digital circuit systems such as FPGAs.In the thesis,the clock distribution circuit is classified into a channel divider module and a clock driver module according to the performance index requirements of the circuit.Each channel in the channel divider module has its own programmable divider and duty cycle correction circuit,which divides the input clock signal,phase delay,and duty cycle correction.With the improved programmable counter as the core,the programmable divider generates mode control signals through the pulse half divider and the configuration number generator to implement the self-release of set numbers and control the working state of different counting units,which further expands the division ratio range.The single divider successfully achieves the integer division from 1to 32.In addition,the divider also provides the phase delay adjustment function in steps of the input clock period and the correction function of the odd division duty cycle.The clock driver module uses the fully differential structure to increase the circuit’s anti-interference capability and the multiplexed amplifier circuit to increase the output signal drive capability.It provides two output level options,LVPECL and LVDS,providing an output reference clock for digital systems with low skew and jitter requirements.The design uses the 0.35μm sige process.The clock distribution circuit uses the cadence specter simulation environment for Pre-simulation and Post-simulation,with an operating temperature range from-55℃ to 125℃.The results of the Post-simulation show that the LVPECL channel operates at the highest frequency of 2.5GHz and can achieve 1 to 32 integer frequency division with an output waveform duty cycle of less than 50±0.5%,an inter-channel skew of less than 0.6ps,and additional jitter of less than44 fs.The LVDS channel operates at the highest frequency of 1.6GHz.It can achieve (1～32)×(1 ～ 32)integer frequency division with an output waveform duty cycle of less than 50±0.5%,an inter-channel skew of less than 1.2ps,and an additional jitter of less than 78 fs.