The Research And Design Of CMOS Charge-Pump Phase-Locked Loop

Phase locked loop circuit(PLL) is a system of frequency or phase tracking, moreprecisely, a kind of system which make output signal synchronize reference inputsignal in frequency and phase, which is an important role in the module in analogand digital mixed circuits. Because of some features of PLL, such as capturing,tracking and filtering, it is used in communication, microprocessor, satellite andother areas. PLL is a most important module in communication clock circuits. Alongwith the development of modern integrated circuit technology, SOC design become amainstream, and PLL become an indispensable basic module in modern very largescale integrated circuit design, so the research and design on PLL are positive realitysignificance.The Charge-Pump (CP) Phase-Locked Loop (is shorted for CPPLL), is a typicalrepresentative in analog and digital mixed PLL, its advantages are followed: CPPLLstatic phase error is zero, fast speed, low power consumption, low jitter and so on.CPPLL is a simple and high effective method in design and implement circuits.A universal Charge-Pump circuit is designed in this thesis, which is applied inPLL, then the research and design of process on CPPLL is introduced. Firstly,CPPLL basic principles are introduced in this thesis, and then analyze themathematical model of CPPLL. Deeply analyze tracking, capturing, stability, noiseand other performances in CPPLL. This thesis introduces mainly the workingprinciple, research and design process of the modified CP. Finally, describes thedetailed research and design process of many devices, which are simulated andlayouts are designed by Cadence. The simulation results demonstrate that the circuitcan quickly lock and steadily work.