Design And Analysis Of Low Noise Charge Pump Phase-Locked Loop Circuit

PLL is developing rapidly, that make it to be the most important core technology of current analog IC. As the most widely used module in communications system, the PLL clock is much useful in a high speed processor. Processors, such large scale digital circuits, in its turnover process will have a serious power noise and substrate noise, further more, the inherent noise of the devices in processors also has great impact on phase locked loop. Aimed at charge pump PLL, the paper analysis the theory deeply, and how to reduce the noise of PLL from the view of system, and established the noise transfer function of the PLL loop, then identified loop parameters and system architecture. It also discussed about how to determine the parameters of the system according to the response speed, stability, and the capability for noise suppression. In another hand the module had been optimized to reduce the noise in PLL. The dead zone of PFD, the current match of charge pump, charge sharing issues, on chip spiral inductors are studied deeply. By adopting the top-down method, a CMOS low noise charge pump phase locked loop is designed. According to the requirements performance indicators are set. From the system design, circuit design to layout design, PLL is completed, and eventually realized by the IC chip fabrication. Generating high speed and stable clock signal is the objective of this subject.