The Key Technologies Of On-chip Resonant Clock Distribution Network With Low Skew And High Energy Efficiency

Clock desitribution network plays an important role in the synchronous circuitsystem, which not only determines the correct function of synchronization system, butalso impacts the system performance, and contributes one of the main components ofpower consumption in the whole system.This dissertation focus on the two key issues of clock distribution network forhigh-performance synchronous system: timing uncertainty and low-power design. Viain-depth study of the emerging on-chip resonant clock technology, a clock distributionscheme based on bufferless resonant clocking is proposed, and the theory of themechanism and key circuits are researched in details. The present bufferless resonantscheme and corresponding design method can not only minimize the powerconsumption in local clock distribution, but also improve the robustness of clock skewover parasitic difference and PVT variations. Moreover, it can meet the requirements oflarge-scale, high-performance synchronous system or complex system with multipleclock domains, and provide a resonant clock distribution with low power dissipation,low skew and low jitter.The main research achievements and innovations described in this dissertation aresummarized as follows:1. A novel strategy to minimize power consumption in local bufferless resonantclocking network is proposed. Targeting at the problem of power minimization inbufferless resonant clocking distribution, a heuristic optimization algorithm is proposed,which trades-off the key design parameters through SPICE analysis, including the clockload, on-chip inductor, clock interconnection network, and energy compensating cell.The optimization algorithm is carried out on the standard benchmark circuits withdifferent sizes. Simulation results show that the power optimization strategy can quicklyconverge and effectively reduce the power consumption in the bufferless resonantclocking network.2. A novel hierarchical bufferless resonant clock distribution network--HBRCDNis proposed for low clock skew and high tolerance to variation. Aims at the skewoptimization and robustness in bufferless resonant CDN, a hierarchical structure ispresented, which combines the advantages of H-tree type and mesh-type together: beingwith the balanced path delay of H-tree while employing multi-fanout parallel paths ofmesh architecture. Simulation results show that, HBRCDN not only reduces the skew inresonant clock network and avoids the impact of unbalanced load, but also behavesgood robustness to the PVT variations. The proposed architecture is verified underTSMC65nm standard CMOS process technology. 3. Targeting at the global design problem for large scale synchronous system, anovel resonant clocking structure with local close coupled network is presented. Firstly,the whole synchronous system is divided into several local regions, which have nearlythe same target frequency and low clock skew by employing HBRCDN structure. Theadjacent clocking networks are injection-locked to each other by on-chip couplingnetwork. Based on the theory of coupled oscallitor array, the frequency and voltagequality are studied systematically. Design and analysis are carried out through anopensource microprocess core. Simulation results show that, the close coupled resonantdistribution structure not only retain the characteristics of low power, low skew andjitter in bufferless resonant clock network, but also be easy to lock, and can providestable clock signals for high-performance synchronous system.4. A novel hybrid resonant clock mechanism is proposed for multi-clock domainsystem. The structure uses traveling wave oscillator array for the global square-wavedistribution network, and makes use of single HBRCDN or multiple close coupledHBRCDNs in each clock domain for low skew and jitter resonant clock. An improvedtraveling wave oscillator--PPTWO is presented to form an array. The global travelingwave signals are then adjusted by clock skew compensation circuit and phase-locked inlocal network by injection locking circuits. Compared with the H-tree structur based oninjection locking global resonant clock distribution, the hybrid resonant clockmechanism not only satisfy the needs of increasing scale of the global clocking, but alsominimizes the power consumption in the local clock network.In summary, the on-chip bufferless resonant clocking techniques for high-perfor-mance digital systems are systematically studied in this dissertation. In order to resolvethe problems such as high designing complexity, being sensitive to parasitic differenceand PVT variations, and limited for large scale synchronous circuits, a serious of novelcircuit techniques and design methodologies are proposed. Moreover, the correctnessand efficiency of the presented techniques and methods are verified thoroughly bytheoretical derivation and experimental simulations. The theoretical and simulationresults show that the techiniques and methods can effectively reduce the powerconsumption in the clock network, and provide high frequency, low-skew and low-jittersynchronous signal for the entire system.The achievements presented in this dissertation have academic and practicalengineering value to promoting the research and application of on-chip resonant clocktechniques for high-performance digital systems.