A Research On Clock And Data Recovery Based On LVDS Interface

With the rapid development of electronic technology and the increasing operating speed of the processor, the high-speed link of transmitter and receiver system will become the trend of the future in a variety of different applications, at this stage there are a variety of applications to be chosen by designers such as Gigabit Ethernet, Fiber Channel, USB 2.0, IEEE1394, SATA bus or other forms of serial link, and the rate of transmission in most systems have reached the level of Gb/s. With the constant increase of the operating frequency, the difficulties faced within the various serial system design are also increasing, including the processing of high-frequency noise which added to transmission channel and the sampling clock generation in the receiver side, this paper will discuss a time oversampling structure-based clock recovery program, the data transform using 8B10B coding scheme, the data stream was coded and transceiver in the EP2C20 FPGA platform based on LVDS channel,by such a structure,using the scheme of 5 times high-speed sampling to detect data edge, it is possible to eliminate the data jitter superimposed in the channel during transmission, thereby eliminating the glitch, and synchronization recovery the same phase clock of the sending end at the receiving side, to get ensure of the tracking performance from the transmitting side.