Design Of A Serial LVDS Transceiver Chipset

As a result of the Internet tremendous growth, data transfers are increasing dramatically in all areas of communications. Low voltage differential signal (LVDS) technology can guarantee Gbps data transmission by adopting analog circuit. Serial data transceiver makes the transmission system quicker while less costly.This dissertation presents the principle, circuit design and layout rules of serial data transceiver which bases on the LVDS transmitter and receiver. The whole circuit, which can be divided into transmitter part and receiver part, is simulated to make sure of its functions in a wide range of 250MHz~800MHz of serial data rate. Transmitter part includes PLL (Phase Locked Loop) cell and serializer cell. Receiver part introduces the method of widening the clock frequency bandwidth of self correcting data clock recovery (CDR) circuit and the design of the circuit of synchronizing the byte clock with 8 parallel data in deserializer. LVDS output stage uses the feedback to control the common-mode voltage in driver design, while its input stage chooses a circuit with extensive input common-mode voltage as well as simple structure including the fail-safe circuit. Finally, some layout principles and issues are discussed.The chip design is based on CHRT .35μm. After layout designed and simulated by Cadence Spectre, the whole design achieves the desired functions and electric characteristics. The chip has 26 pins with power comsumption of 900mW at the serial data rate under 800MHz.