Uwb System Clock Circuits And Design

The ultra-wideband (UWB) system has expansive market applications due to itsoutstanding advantages.A deep research of monolithic CMOS frequency synthesizerfor MB-OFDM UWB receiver is presented in several aspects in this thesis.Firstly,a review of the history about UWB communication development is given.The fundamentals of MB-OFDM UWB system are introduced.The designspecifications of the frequency synthesizer are deduced.Based on the analysis andcomparison of different architectures,the dual-PLL architecture is selected to be themost approximate one.Secondly,system design of the fourth-order phase-locked loop is introduced.ThePLL system model and parameter design flow are given.The relationship of the loopstability and open loop bandwidth is discussed.Each individual noise model of thePLL building blocks and the overall phase noise at the PLL output are presented.Anadaptive frequency calibration (AFC) design method for PLL is proposed.Thirdly,the profound theoretical analysis of theΣΔmodulator for thefractional-N PLL is presented,which includes theΣΔquantization noise,therequirement of the PLL bandwidth,the impact of the charge pump current mismatchto phase noise,and the method of suppressing theΣΔquantization noise.The analysisgiven here has a strong guidance to the circuit designers.Fourthly,the design of the voltage-controlled oscillator,which is the mostimportant building block in PLL,is analyzed and discussed.The content incorporatesthe circuit architecture,performance parameters,spiral inductor and varactor,thephase noise model,and the phase noise optimizing technique.Then the quadraturesignal generation technique is given.Finally,the design of a fast hopping CMOS frequency synthesizer for"mode 1"MB-OFDM UWB system in 0.13μm CMOS process is presented.The die photographis given.The experimental results show that the reference sidebands of both PLLs(2.112GHz and 3.96GHz) are smaller than -60dBc.The spot phase noise is betterthan -ll0dBc/Hz on 1MHz frequency offset.The in-band spur is smaller than-30dBc and the out-of-band spur is smaller than -50dBc.Other measurementperformances also meet the design specifications.Then the system architecture andcircuit design of another fast hopping 8-band frequency synthesizer are presented.