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Study Of 10bit-55Msps Pipelined ADC In Channel Demodulation Chip For Digital TV

Posted on:2010-08-09Degree:MasterType:Thesis
Country:ChinaCandidate:S X CaoFull Text:PDF
GTID:2178360275473120Subject:Microelectronics and Solid State Electronics
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With the rapid development of information society, the digital TV has been one of the focuses of attention in information industry. The demand for Set-Top Box, HDTV receiver and USB dongle is increasing day by day, in the process that the analog TV transits into the digital TV. As the important module of digital television channel receiver and demodulation system, ADCs convert the RF or IF signal into digital signal, and it is needed that ADCs have higher sampling speed, higher resolution, higher SFDR and good SNR.In this dissertation, a 10bit 55Msps pipelined ADC used in DMB-T/H digital TV channel demodulation chip is designed in SIMC 0.18μm 1P6M CMOS process. The ADC operates with a 3.3V/1.8V power supply, and the whole circuit is comprised of 9 stages, all in 1.5bit per stage except for the final stage which is in 2bit per stage. While two groups of six-phase non-overlapping clocks are generated to operate neighboring pipelined stages. Besides, a gain boosted folded-cascode OTA with SC-CMFB circuit is used in S/H and MDAC circuits because of the high DC gain and high bandwidth. And a differential SC dynamic comparator is designed for sub-ADC, which has high speed and small offset voltage. In design of peripheral digital circuits, C~2MOS edge-triggering flip-flop is used in order to ensure the digital codes delayed and aligned and 1bit full adder is used for digital correction circuit. At the same time Gate-voltage bootstrapped switch, sub-DAC, clock generator, reference current distributing circuit, a variety of driving circuits; buffers and so on are also designed in detail.In this dissertation, emphasis is put on the transistor-level circuits design and simulation. All designed circuits are simulated with Spectre of Cadence, then the simulation results are obtained through Fast Fourier Transform using Matlab tool in order to get power spectrum of output signal. The simulation results eventually show that the ADC has static performance within +0.5LSB and dynamic performance above 60dB, which meet the demands of DMB-T/H terrestrial digital TV channel demodulation system.
Keywords/Search Tags:Digital TV, Channel Demodulation, Analog-to-Digital Converter, Pipelined, Gain-boosted, Dynamic Latch
PDF Full Text Request
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