| With high-speed development of digital technology, especially the powerful ability in signal and data processing of digital circuit due to the digital computing and signal processing technology. So, it is becoming more and more common to deal with analog signal with digital circuit. But, in order to do this, analog signal should be transfer to digital signal first. As the interface of analog signal and digital signal, analog to digital converter (ADC), plays a more and more important roal.The design target of this thesis is a 12-bit resolution with 100Ksps throughout rate successive approximation (SAR) analog to digital converter. Power supply range from 2.7v to 3.6v, the max power dissipation is 1.8mW. High resolution, low power dissipation, small dimension is the primary goal of this design.DAC is a key component of the SAR ADC. We choose the two stage charge redistribution structure to meet the requirement of low power dissipation and high resolution. After studying the relationship between the accuracy of the total DAC and the accuracy of the two subdacs, as well as the match characteristic of the process. We decide the optimum resolution of the two subdac is 4 and 8, respectively.Comparator is another key component of the SAR ADC. Beyond the requirements of accuracy and speed should be met, power dissipation should be as low as possible. The comparator is consisted of milt-peramplifier and a high gain amplifier, combining with output offset storage technology.The capacitor array of two stages DAC is shared by sample/hold circuit as sample capacitor. The bottom sampling technique and full differential technique are applied to improve the accuracy.Every circuit is simulated after design was finished. The simulation results show that the circuit satisfys the design target well.The layout design was finished. When passed DRC and LVS, get the netlist includes parasitic parameters to make post simulation, the simulation results also show the circuit satisfy the design target well. |
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