Font Size: a A A

Research And Design Of 12-bit Successive Approximation Analog To Digital Converter

Posted on:2008-12-26Degree:MasterType:Thesis
Country:ChinaCandidate:X Y WangFull Text:PDF
GTID:2178360215465004Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
In the front and the end of the advanced electronics systems, analog to digital converters (A/D converters) are applied to use completely the perfect performance of the digital processing technique to process the analog signal. Of all kinds of A/D converters, successive approximation (SAR)A/D converters are frequently the architecture of choice for medium-to-high-resolution applications, SAR A/D converters have a wide variety of applications, such as portable/battery-powered instrument,pen digitizers, industrial controls and data/signal acquisition.A 12bit SAR A/D converter is designed in this thesis. The sample/hold circuit in the A/D converter is based on recycling architecture which has small pedestal error, high linearity and high speed, Folded-cascade architecture is used for the operational amplifier in the sample/hold circuit, and this kind of amplifier had a high voltage gain and good high-frequency power-supply rejection ratios from the Vee supply; DAC is constituted by combining the segmented current-steering DAC and R-2R network current-steering DAC altogether, and the DAC has a high speed because of no using the operational amplifier; The bandgap circuit is a 10V on-chip voltage bandgap which is based on Brokaw architecture and performs one-order temperature compensation, which is very important for the stability of the tail current in DAC. Compared with MOS device, bipolar transistors exhibit superior threshold matching, higher transconductance, and lower noise level. A current-switching bipolar comparator which consists of pre-amplifier and a regeneration latch is adopted to achieve high speed and high precision. The simulation results show that the comparator exhibits fast response and high precision. Non-ideal factors in SARADC are analyzed and some methods to decrease these non-ideal factors are presented.All circuits are designed in BiCMOS technology and simulated in spectre. The results of simulations indicate these cell circuits can meet the requirements of the system.
Keywords/Search Tags:SAR ADC, sample/hold, bipolar latch comparator, DAC
PDF Full Text Request
Related items