Design Of Fractional Divider For ΔΣ Fractional-N Frequency Synthesizer

With the development of modern communication technology, frequency synthesizer is becoming more and more important. The high quality local oscillation signal which is essential to any communication system relies on properly designed frequency synthesizer. In all kinds of synthesizers, the fractional-N frequency synthesizer adoptingΔΣmodulation technology has become the mainstream of design and application, for its outstanding performance of lower phase noise and frequency resolution.A fractional divider used in 1.81G Hz~1.93G Hz fractional-N frequency synthesizer is designed in this paper. The fractional divider which distinguishes fractional synthesizers from integer ones, is the key module of fractional-N synthesizer and composed ofΔΣmodulator and multi-modulus frequency divider. A 3rd-order Single-LoopΔΣmodulator is designed in this paper with -158dBc/Hz quantization noise suppression at low frequency and -120dBc/Hz phase noise of whole synthesizer output at 900 kHz. SCL (Source Couple Logic) prescaler, Phase Switching (Pulse Swallowing) dual-modulus (7/8) divider and Programmable Counter are included in multi-modulus divider, which can work under the input of 2G Hz and cover the division modulus range of 64~84, or even larger when needed. In this design, an improvedΔΣclock setting are also depicted, which successfully avoids two problems arisen by traditionalΔΣclock settings: wrong fractional division ratio and influence ofΔΣmodulator to phase-detection of PFD (Phase Frequency Detector).The whole design is implemented by Chartered 0.35um RF CMOS process, and successfully meets the demand of fractional-N frequency synthesizer.