Video Analog Front-end Ip Core Design, The Standard Digital Cmos Process

The main function of the video analog front end (VAFE) is filtering, amplifiering and quantifying the video signals to make them processable for the digital signal processors. VAFE is widely used in custom circuits such as digital cameras, digital television and monitors. These kinds of products have large market now, so designing highly compatible VAFE with high performance, high resolution and low power is largely required. This dissertation mainly investigates the design of configurable VAFE intelligence patent (IP) core with high speed, high resolution and low power.A 10-bit, 100 MS/s VAFE is designed in this thesis. The main modules of this VAFE are clamp, low pass filter (LPF), and a pipeline analog digital converter (ADC) which integrates a programmable gain amplifier (PGA). The relationship between the performance of the main modules of the VAFE and that of VAFE as a whole is analysed in the dissertation. Based on the analysis, the main modules are configured respectively.The author proposed charge-pump-structured clamp circuit which satisfies the requirement of the VAFE. The digital signals decide the output current of the charge pump which achieves high speed and high resolution performance. In order to satisfy the requirement about the bandwidth of the video signals, this dissertation proposes a tunable low pass filter, whose largest bandwidth is 40 MHz. The bandwidth of the LPF can be tuned by changing the variable resistor arrays.A 10-bit 100 MS/s pipeline ADC is designed in this dissertation. This ADC integrates a PGA to make its gain tunable. In this ADC, staggered metal finger (SMF) capacitor and common plate metal finger (CPMF) capacitor substitute MIM capacitor, and achieve almost the same performance as the MIM capacitor. Design techniques such as symmetric bootstrapped switch, bulk-switching switch and operational amplifier with thin-gate input transistors are used to enhance the linearity and reduce the power of the ADC. The ADC is designed in TSMC 0.18μm 1.8/3.3V CMOS pure logic process, occupies 2.7 mm~2 and consumes 53mA for 100-Ms/s operation. The dynamic range of the input differential signal is 2V. The signal-to-noise-and-distortion ratio (SNDR) is 48.7 dB for a full-scale sinusoidal input, respectively. The author improves the circuits based on the research of the test results of the ADC and integrates the ADC. with the clamp and LPF to make a complete VAFE IP core. The layout of this IP core has been completed.