Analysis And Design Of RF Oscillator And PLL Architecture

Oscillators are an integral part of many electronic systems. Applications range from clock generation in microprocessors to carrier synthesis in cellular telephones, requiring vastly different oscillator topologies and performance parameters. Robust, high-performance oscillators which are designed in CMOS technology are usually embedded in a phase-locked system. As one of the most widely used modules, PLL has broad application in high speed processor clock generation.With the development of integrated circuit technology, typical dies size has reached deep sub-micrometer, and typical voltage has already lower than 1V. The balance between power dissipation and circuit performance is a serious problem with the effect of noise.This paper studies the models of high speed and low power oscillators, analysis their parameters, then, proposes a low power and low phase noise RF LC VCO.At the same time, this paper studies kinds of architectures of PLL's models, compares their performances and analysis the technology parameter, then, proposes a high-performance charge pump PLL which provides stable clock for the analog and digital mixed chip.A high-speed PFD that meets the requirement specified by overall performance of the PLL is designed. The PFD has fine phase-detection ability while consuming very low power. Its operation speed is improved by making use of true single phase clock (TSPC)-based flip-flop. A high phase-detection resolution is desirable for a PFD. This paper also discusses the foundation knowledge of the design of the LPF, and then calculates the circuit parameter with the model.The circuit of PLL is laid out. A simple introduction to the manufacturing process is performed, then factors being taken into consideration in floor planning and routing the circuit are discussed. The lay-out of each module and back-end simulation results are also given.The charge-pump phase-locked loop designed in this paper is fully-customized, and it is to be taped out with standard mixed signal 0.18μm provided by IBM. The area of the final PLL layout is 74×115μm~2...